ESA – RTG4 FPGA SEE Mitigation

Flash-based FPGAs are relatively new products in the portfolio of space-grade FPGAs and the development flow for space-related requirements is not fully proven yet through extensive learning and customer feedback dynamics.

Although not initially developed for space harsh-environment, Microsemi’s 3^rd product generation of flash-based FPGAs, known as IGLOO2 and PROASIC3, are widely used in space applications thanks to the radiation tolerance of the flash-based configuration and the implementation of specific design technics against radiation effects. The 4^th generation (RT Polarfire and RTG4) intended for conventional space applications such as high-performance on-board computing and high-bandwidth data processing payload, already implements rad-hard high-performance programmable resources, digital, memories, PLL, and I/O interfaces. Automatic execution of SEU mitigation techniques and SET filtering is allowed through Synthesis and Place & Route tools, respectively.

Since these devices are relatively new, their space heritage and radiation data are quite limited compared to other more mature solutions like Microsemi’s RTAX anti-fuse family. The proper implementation of SEU and SET mitigation techniques is difficult to confirm and verify in an automatic and thorough manner, since formal verification EDA tools, such as Synopsys Formality and Mentor Formal Pro, cannot confirm logic equivalence of a rad-hard design against its unmitigated counterpart, and verify its proper implementation in the specified areas. This could lead to potential design weaknesses and unexpected failures under radiation. On the other hand, former studies led by Airbus Defense & Space in collaboration with NASA/GSFC have shown SEE radiation sensitivity on RTG4 FPGA fabric and configuration cell re-programmability.

To better understand Microsemi’s 3^rd and 4^th generation of flash-based FPGAs and their performance against radiation, ESA issued a contract to ARQUIMEA with the following objectives:

• Development of rad-hard IP-cores with custom SEU/SET mitigation techniques applied at RTL/Netlist level to allow comparison with a reference unmitigated version
• Performance of an extensive radiation test campaign, targeting the 4^th generation flash FPGAs from Microsemi (RTG4 in particular) to verify the fabric hardness and effectiveness of complementary custom SEU/SET mitigation techniques.

The activity required the development of several complex test vehicles on the RTG4 FPGA to validate the impact under heavy-ion and proton radiation of the FPGA fabric and SEU/SET mitigated designs compared to their unmitigated counterparts. In addition, the planning constraints and the potential damage of RTG4 FPGAs due to back-grinding operations or electrical failure were considered as the main risks of the project.

ARQUIMEA led a consortium that carried out the design of rad-hard integrated circuits running on the RTG4, as well as verification tools to prove the equivalence of the designs with and without SEE mitigation techniques. The devices were validated under radiation using ARQUIMEA’s own proprietary SEE test setup.

Two SEE campaigns were conducted on the RTG4 FPGA under heavy ion and proton in November 2019. The measurements confirmed the results from Microsemi and NASA/GSFC. Nonetheless, the following behavior were observed:

• The SET filtering improves cross-section only at lower LET energies and higher frequencies
• The tested pads present SET, sometimes well over 10ns width
• The PLL presents SET and SEFI with cross-section and LET threshold acceptable for most of the space applications
• The FPGA SERDES shows sensitivity to radiation with degraded BER at low LET and a complex scenario of SEFIs.

Disclaimer: The view expressed herein can in no way be taken to reflect official opinion of the ESA.